STM will provide experimental data on planar FDSOI transistors. LETI will focus on tri-gate and gate-all-around architectures on SOI substrate, fabricated in collaboration with STM. Most of the needed experimental data is already available. For instance, LETI has recently performed extensive electrical characterization of W-gate NMOS and PMOS silicon transistors, with different channel lengths, crystal orientations, and strains.
The NW transistors are processed on 300mm SOI and sSOI substrates with a 145nm buried oxide. WNW and LG scaled down to 8nm are achieved. The Si thickness (NW height: HNW) under the HfSiON/TiN gate is around 11nm. During the project, the silicon thickness varying from 7nm up to 25nm will be available. The nanowire width WNW and the gate length LG will be measured from spectroscopic ellipsometry, SEM, and TEM images.
The effect of uniaxial tensile strain in Tri-gate/Omega-gate NW FETs will be investigated, discussed and compared to theoretical results. Strained-Si NW N-FET will be fabricated by lateral strain relaxation of sSOI substrates.
All existing samples will be used to validate completely the simulation tools. We aim to show that quantum simulations predict accurately the influence of the main technological parameters: geometry, material channel, channel orientation, strain, source/drain epitaxy (SiGe, silicides), back gate. The validation will go beyond the electrical characteristics of the channel: the ability of the models to describe thermal dissipation contact resistances and capacitances will be also carefully analyzed.
Predictive simulation for the design of new devices
We will then introduce quantum simulations into the design workflow of new tri-gate architectures on SOI substrate, and to demonstrate a full simulation-fabrication-characterization cycle by the end of the project. The current design workflow is mainly based on compact modeling of small circuits such as ring oscillators and SRAMs. The figures of merits depend on the electrical performances and on extrinsic effects (resistances, capacitances). Accurate compact models are available for planar devices, but not for multi-gate architectures.