This task is devoted to provide analytical expressions to be included in compact models for MOSFET and Tunnel-FET currents, as well as circuit metrics able to serve as realistic guidelines for industrial actors. A subtask is also dedicated to the quantum modelling of elementary circuits (i.e. inverter and SRAM) by connecting NW-MOSFETs and Tunnel-FETs within the NEGF formalism.
Calibration of analytical models for rapid simulation of devices
We plan to develop and calibrate analytical models able to account for the on state current of nanoscale devices analyzed in this project such as Tri-gate, NW and III-V MOSFETs. The quasi-ballistic Lundstrom model will be used to adjust the backscattering coefficient, on both long and short scale carrier transport. For the off state, analytical models of the channel potential will be used to capture the impact of short channel effects and tunneling leakage (source-to-drain tunneling and band-to-band tunneling). The analytical modelling of band-to-band tunnelling will require careful benchmark on the advanced simulators developed in Task 4.
Further, we will develop top-of-the-barrier models providing a reasonable description of the electrostatics and ballistic current of short channel MOSFETs. They are simply based on the self-consistent band structure of the cross section of the channel at the top of the barrier (most limiting point), which can be computed in a few seconds on standard workstations. Such Top-of-the-barrier solvers will be built upon atomistic tight-binding or k.p solvers.
Simulation of simple circuits via analytical models
We will work on the implementation into MASTAR of new analytical models describing the electrostatics of III-V-based Double Gate MOS structures. A specific implementation into MASTAR VA, the Verilog A version of MASTAR compatible with conventional CAD tools, will be carried out.An evaluation of realistic loaded Ring Oscillator (NAND & Inverters), Critical paths, and 6T-SRAM bit cells performances will be done.
Study of quantum transport in simple circuits
Finally, we will model elementary circuits through the coupling of few transistors within the NEGF formalism. The first stage will be to model an inverter (NOT gate) using two complementary transistors (p-type and n-type) in a CMOS configuration. Inverter quality is often estimated using the Voltage Transfer Curve (VTC), which is a plot of the input versus output voltages. Ideally, the VTC appears as an inverted step-function, but in real devices, a gradual transition region exists. The slope of this transition region is a measure of quality: steep slopes yield precise switching. From such a graph, device parameters including noise tolerance, gain, and operating logic-levels can be obtained. We will then investigate the quantum effects occurring in such a circuit at room temperature and evaluate the impact on its performances when random surface roughness and different distribution impurities are incorporated.
This study will represent a pioneering work that fully describes elementary circuits by quantum mechanical NEGF formalism. It will make possible to explore deep quantum phenomena occurring in low dimensionality at the interface between two transistors (confinements, tunnelling, localization).