As promising candidates to replace silicon-based MOSFETs a great effort has been devoted to research on multi-gate nanodevices with III-V channel materials. However, the different technological options with various high mobility channel materials (such as InGaAs or InGaSb) and device geometries (planar versus Tri-Gate) have not yet been sorted. On the other hand alternative devices with steep subthreshold slopes such as Tunnel-FETs are also very promising for the semiconductor industry (represented in this project by ST Microelectronics). We will investigate transport properties for these devices and estimate variability limitations at small supply voltages.
k.p and Kubo-Greenwood model parameterizations
Our teams have a strong track record on tight-binding model calibration based on ab-initio calculations. In this part we aim to establish a database of the k.p parameters of the principal III-V materials. If necessary, we will refine the tight-binding models (in particular the description of strains) using ab-initio calculations. As an alternative approach, we will exploit atomistic empirical pseudo-potential methods to determine full bandstructure curves and to calibrate 8-band k.p Hamiltonians for III-V nanostructures.
Transport properties of III-V nanowires and films
This part focuses on the transport properties of III-V nanowires and films with respect to Si and Ge. We will perform predictive simulations based on a rigorous treatment of quantum confinement, tunnelling, discrete charged and neutral defects, and phonon scattering.For this purpose, we will address 3D self-consistent simulations of III-V MOS transistors based on advanced physical models within the Keldysh-Green’s function formalism on top of 8-band k.p Hamiltonians. First purely electrostatic simulations will be performed in order to identify the most promising couples of material and device architecture in terms of short-channel effects. Second, we will perform a systematic analysis of the transport properties of the selected devices, and address different crystallographic orientations and stress configurations.
Mobility is an important factor of merit in nano-transistors. We will then investigate the influence the scattering mechanisms (i.e. phonons, impurities, roughness…) on carrier mobility
Finally, in order to match the industrial requirements for the 10nm node, we will investigate the overall performances of such devices by means of TCAD numerical simulations, and compare them to Si or SiGe-based present solutions.
Transport properties of III-V steep-slope devices
Alternative devices like Tunnel-FETs based on III-V materials are expected to be much more promising for low power applications with respect to Si or Si/Ge Tunnel-FETs due to their small energy gap and effective masses.
Based on calibrated k.p Hamiltonians previously obtained, III-V homo-junction and hetero-junction NW Tunnel-FETs will be investigated and optimized by means of 3-D self-consistent simulations within the Keldysh-Green’s function formalism. In particular, we will exploit 8-bands k.p Hamiltonians to study, optimize and assess heterojunction Tunnel-FETs based on InAs (operating as n-type devices) and then heterojunction Tunnel-FETs based on InAs and a few ternary compounds, such as InGaAs and/or InAlAs or GaSb with appropriate stoichiometric parameters (operating as both p-type and n-type devices). The effect of strain will be investigated to identify favorable configuration.